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Da t as heet
AS1524/AS1525
1 5 0 k s ps , 1 2 - B i t , 1 - C h a n n e l P s e u d o / Tr u e - D i f f e r e n t i a l and 2-Channel Single-Ended ADCs
1 General Description
The AS1524/AS1525 are low-power, 12-bit analog-todigital converters (ADCs) designed to operate with a single +2.7V to +5.25V supply. Excellent dynamic performance, low power consumption, and simplicity make these devices perfect for portable battery-powered dataacquisition applications. The devices are available as the standard products listed in Table 1. Table 1. Standard Products Model AS1524 AS1525 Input Type 1-Channel, Pseudo / True-Differential 2-Channel, SingleEnded Input Voltage 0 to VREF / -VREF/2 to VREF/2 0 to VREF
2 Key Features
! ! !
Single-Supply Operation: +2.7V to +5.25V Automatic Shutdown Between Conversions Low Power Consumption - 350A @ 150ksps - 245A @ 100ksps - 24A @ 10ksps - 2.5A @ 1ksps - 200nA in Automatic Shutdown Mode
!
True-Differential Track/Hold, 150kHz Sampling Rate Software-Configurable Unipolar/Bipolar Conversion (AS1524) Input Common Mode Range from GND to VDD 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Internal Conversion Clock 8-pin TDFN (3x3mm) Package
The devices feature a successive-approximation register (SAR), automatic shutdown, fast wakeup (1.4s), and low-power consumption at the maximum sampling rate of 150ksps. Automatic shutdown (0.2A) between conversions results in reduced power consumption (at slower throughput rates). Data access are made via an external clock through the SPI-/QSPI-/MICROWIRE-compatible 3-wire high-speed serial interface. The AS1525/AS1524 are available in a 8-pin TDFN (3x3mm) package.
! !
! !
3 Applications
The devices are ideal for remote sensors, data-acquisition, data logging devices, lab instruments, or for any other space-limited A/D devices with low power consumption and single-supply requirements.
Figure 1. AS1524/AS1525 - Block Diagram
1 VDD 7 CNVST 8 SCLK Control Logic 2 AIN1/AIN+ 2 AIN2/AIN4 REF 5 GND Track/ Hold 12-Bit SAR 6 DOUT Input Shift Register
AS1524/AS1525
Osc
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AS1524/AS1525
Datasheet
Contents
1 General Description 2 Key Features 3 Applications 4 Pinout ............................................................................................................................. 1
........................................................................................................................................ 1 .......................................................................................................................................... 1
................................................................................................................................................... 3 ..................................................................................................................................................... 3
................................................................................................................................................... 3
Pin Assignment Pin Description
5 Absolute Maximum Ratings 6 Electrical Characteristics
Timing Characteristics
................................................................................................................. 4
...................................................................................................................... 5 ........................................................................................................ 8
.......................................................................................................... 11 .........................................................................................12
......................................................................................................................................... 7
7 Typical Operating Characteristics 8 Detailed Description
........................................................................................................................... 11
...................................................................................................................... 11
True Differential Analog Input Track/Hold Selecting AIN1 or AIN2 (AS1525) Input Bandwidth Internal Clock
Selecting Unipolar or Bipolar Conversions (AS1524) Analog Input Protection Output Data Format Transfer Function
..................................................................................................................................................13 ......................................................................................................................................13 ......................................................................................................................................................13 ............................................................................................................................................13 ................................................................................................................................................13
9 Application Information
External Reference
....................................................................................................................... 15
.................................................................................................................................15 ....................................................................................................................................15
Automatic Shutdown Mode Performing a Conversion
.............................................................................................................................................15
Standard Interface Connections ..........................................................................................................................15 SPI and Microwire Interface ........................................................................................................................... 15 QSPI Interface ................................................................................................................................................16 PIC16 and SSP Module and PIC17 Interface ................................................................................................17 Layout and Grounding Considerations .............................................................................................................. 19
10 Package Drawings and Markings 11 Ordering Information
.................................................................................................... 20
........................................................................................................................ 21
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AS1524/AS1525
Datasheet - P i n o u t
4 Pinout
Pin Assignment
Figure 2. Pin Assignments (Top View)
VDD 1
8 SCLK
AIN1/AIN+ 2
AIN2/AIN- 3
AS1524/ AS1525
7 DOUT
6 CNVST
GND 4
5 REF
Pin Description
Table 2. Pin Description Pin Number 1 2 3 4 5 Pin Name VDD AIN1/AIN+ AIN2/AINGND REF Description Positive Supply Voltage. +2.7V to +5.25V. Note: Bypass with a 0.1F capacitor to GND. Analog Input Channel 1 (AS1525) or Positive Analog Input (AS1524) Analog Input Channel 2 (AS1525) or Negative Analog Input (AS1524) Ground External Reference Voltage Input. Sets the analog voltage range. Note: Bypass with a 4.7F capacitor to GND. Conversion Start. A rising edge powers up the device and puts the track/ hold circuitry in track mode. At the falling edge of this pin, the device enters hold mode and begins a conversion. Note: This pin also selects the input channel (AS1525) or input polarity (AS1524). Serial Data Output. This pin transitions the falling edge of SCLK and goes low at the start of a conversion and delivers the MSB at the completion of a conversion. Note: This pin goes high impedance once data has been fully clocked out. Serial Clock Input. Clocks out data at DOUT with the MSB first.
6
CNVST
7
DOUT
8
SCLK
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AS1524/AS1525
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter VDD to GND CNVST, SCLK, DOUT, REF, AIN1/ AIN+, AIN2/AIN- to GND Current into Any Pin Continuous Power Dissipation Operating Temperature Range Storage Temperature Range 1491 -40 -60 +85 +150 Min -0.3 -0.3 Max +6 VDD + 0.3 50 Units V V mA mW C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020D "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). TAMB = +70C; derate 19.5mW/C above +70C Comments
Package Body Temperature
+260
C
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AS1524/AS1525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = +2.7 to +5.25V, VREF = +2.5V, 4.7F Capacitor at REF; fSCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1524) TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25C. Unipolar Mode (AS1524). Table 4. Electrical Characteristics Symbol DC Accuracy Resolution INL DNL Relative Accuracy Differential Non-Lineraity Offset Error Gain Error
1
Parameter
Condition
Min 12
Typ
Max
Unit Bits
1.0 No Missing Codes Over Temperature -0.99 1 1 0.3 0.3 0.1 0.1 +1.0 4 4
LSB LSB LSB LSB ppm/C ppm/C LSB LSB
Gain Temp Coefficient Offset Temp Coefficient Channel-to-Channel Offset Match Channel-to-Channel Gain Match
Dynamic Specifications - (fIN (sinewave) = 10kHz, VIN = 2.5VP-P, 150ksps, fSCLK = 8MHz (50% duty cycle), AIN- = GND (AS1524) SINAD THD SFDR Signal-to-Noise Plus Distortion Total Harmonic Distortion (to the 5th Harmonic) Spurious-Free Dynamic Range Full Power Bandwidth Full Linear Bandwidth Conversion Rate tCONV tACQ Conversion Time Track/Hold Acquisition Time Aperture Delay fSCLK Max Serial Clock Frequency Serial Clock Duty Cycle Analog Input VIN Range
2
72.5 -79.5 84 -3dB Point -0.1dB Point Exclusive of tACQ 20 400 3.3 3.7 1.4 30 8 30 Unipolar Bipolar No Channel Selected or Conversion Halted Track Mode Hold Mode 0 -VREF/2 0.01 20 5 VDD + 50mV 11 19 0 +2 +5 25 70 VREF VREF/2 1
dB dB dB MHz kHz s s ns MHz %
V A pF pF
Input Leakage Current Input Capacitance External Reference Input VREF VIN Range
1.0 VREF = +2.5V @ 150ksps
V
IREF
Input Current
VREF = +4.096V @ 150ksps Acquisition Between Conversions
A
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AS1524/AS1525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Electrical Characteristics (Continued) Symbol VIL VIH ILEAK CIN VOL VOH Parameter Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Low Voltage Output High Voltage Tri-State Leakage Current Tri-State Output Capacitance Power Requirements VDD Positive Supply Voltage VDD = +3V, fSAMPLE = 150ksps VDD = +3V, fSAMPLE = 100ksps VDD = +3V, fSAMPLE = 10ksps VDD = +3V, fSAMPLE = 1ksps IDD Positive Supply Current VDD = +5V, fSAMPLE = 150ksps VDD = +5V, fSAMPLE = 100ksps VDD = +5V, fSAMPLE = 10ksps VDD = +5V, fSAMPLE = 1ksps Automatic Shutdown Mode PSR Power Supply Rejection VDD = +5V 5%, Full Scale Input VDD = +2.7V to 3.6V, Full Scale Input 2.7 350 245 24 2.5 485 330 33 3.7 0.2 0.3 0.4 1 mV 550 A 5.25 425 V ISINK = 2mA ISINK = 4mA ISOURCE = 1.5mA CNVST = GND CNVST = GND 0.7VDD 0.05 15 5 0.7VDD 0.01 15 0.4 0.8 1.0 Condition Min Typ Max 0.3VDD Unit V V A pF V V A pF
Digital Inputs/Outputs (CNVST, SCLK, DOUT)
1. Offset nulled. 2. The absolute input voltage range for the analog inputs is from GND to VDD.
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AS1524/AS1525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Characteristics
VDD = +2.7 to +5.25V, VREF = +2.5V, 4.7F Capacitor at REF; fSCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1524) TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25C. Table 5. Timing Characteristics Parameter SCLK Pulse Width High SCLK Pulse Width Low SCLK Falling-to-DOUT Transition SCLK Rising-to-DOUT Disable
1
Symbol tCH tCL tDOT
Conditions
Min 38 38
Typ
Max
Units ns ns
CLOAD = 30pF (see Figure 3, Figure 4, Figure 19 on page 12, Figure 20 on page 12) CLOAD = 30pF (see Figure 3, Figure 4, Figure 19 on page 12, Figure 20 on page 12) CLOAD = 30pF (see Figure 3, Figure 4, Figure 19 on page 12, Figure 20 on page 12) 30 100
28
60
ns
tDOD
200
500
ns
CNVST Falling-to-MSB Vlid CNVST Pulse Width
tCONV
tCSW
3.3
3.7
s ns
1. Guaranteed by Design and Characterisation. Figure 3. DOUT Enable/Disable Time Load Circuits
VDD DOUT 6k CLOAD DOUT GND GND CLOAD 6k
High-impedance to VOH, VOL to VOH, and VOH to High-impedance GND
Figure 4. Detailed Serial Interface Timing Diagram
CNVST
tCL SCLK
tCH
tCSW
tDOT DOUT
tDOD High Z
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AS1524/AS1525
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VDD = 5V; VREF = 2.5V, fSCLK = 8MHz(50% duty), CREF = 4.7F, TAMB = +25C (unless otherwise specified). Figure 5. Integral Nonlinearity vs. Digital Output Code Figure 6. Differential Nonlinearity vs. Digital Output Code
1 0.8 0.6
fSAMPLE = 150ksps
1 0.8 0.6
fSAMPLE = 150ksps
DNL (LSB) .
INL (LSB) .
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 3072 4096
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 3072 4096
Digital Output Code
Digital Output Code
Figure 7. Supply Current vs. Supply Voltage
600 500 400 300 200 100 0 2.7 3.2 3.7 4.2 4.7 5.2
Figure 8. Supply Current vs. Temperature
500 450
150ksps
Supply Current (A) .
Supply Current (A) .
fSAMPLE = 150ksps
400 350 300 250 200 150 100 50
10ksps 1ksps 100ksps
0 -45 -30 -15 0
15 30 45 60 75 90
Supply Voltage (V)
Temperature (C)
Figure 9. Supply Current vs. Temperature, VDD = 3V
360
150ksps
Figure 10. Supply Current vs. Sampling Rate
1000
320
Supply Current (A) .
280 240 200 160 120 80 40 0 -45 -30 -15 0
10ksps 1ksps 100ksps
Supply Current (A) .
100
10
1
0.1
15 30 45 60 75 90
0.01 0.01
0.1
1
10
100
1000
Temperature (C)
Sampling Rate (ksps)
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AS1524/AS1525
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 11. Shutdown Current vs. Supply Voltage
10 9
Figure 12. Shutdown Current vs. Temperature
100 90
.
Shutdown Current (nA)
7 6 5 4 3 2 1 0 2.7 3.2 3.7 4.2 4.7 5.2
Shutdown Current (nA)
8
.
80 70 60 50 40 30 20 10 0 -45 -30 -15 0 15 30 45 60 75 90
Supply Voltage (V)
Temperature (C)
Figure 13. Offset Error vs. Supply Voltage
2
Figure 14. Offset Error vs. Temperature
2
.
.
1
1
Offset Error (LSB)
Offset Error (LSB)
0
0
-1
-1
-2 2.7 3.2 3.7 4.2 4.7 5.2
-2 -45 -30 -15
0
15 30
45
60 75
90
Supply Voltage (V)
Temperature (C)
Figure 15. Gain Error vs. Supply Voltage
2
Figure 16. Gain Error vs. Temperature
2
Gain Error (LSB) .
1
Gain Error (LSB) .
2.7 3.2 3.7 4.2 4.7 5.2
1
0
0
-1
-1
-2
-2 -45 -30 -15
0
15 30
45
60 75
90
Supply Voltage (V)
Temperature (C)
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AS1524/AS1525
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 17. FFT @ 10kHz
0 -20 -40
fSAMPLE = 150ksps NFFT = 32768 SNR=72.7dB THD = -79.3dB SFDR = 83.5dB
FFT (dBC) .
-60 -80 -100 -120 -140 -160 0 15 30 45 60 75
Input Signal Frequency (kHz)
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AS1524/AS1525
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1524/AS1525 employ a successive approximation conversion (SAR) technique and integrated track/hold circuitry to convert analog signals into 12-bit digital output. The serial interface provides easy interfacing to microprocessors. Figure 18 shows the simplified internal structure for the AS1525 (2-channels, single ended) and the AS1524 (1-channel, true differential).
True Differential Analog Input Track/Hold
The equivalent circuit of Figure 18 shows the device input architecture which is composed of track/hold circuitry, input multiplexer, comparator, and switched-capacitor DAC. The track/hold circuitry enters its tracking mode on the rising edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (AS1525) or AIN+ (AS1524). The negative input capacitor is connected to GND (AS1525) or AIN- (AS1524). Figure 18. Equivalent Input Circuit
REF 12-Bit Capacitive DAC GND AIN2 AIN1/AIN+ CIN+ + Hold CIN- GND/AINRINHold VDD/2 Track RIN+ Comparator Hold
The track/hold circuitry enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted. The time required for the track/hold to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and CNVST must be held high for a longer period of time. The acquisition time (tACQ) is the maximum time needed for the signal to be acquired, plus the power-up time. tACQ is calculated by: tACQ = 9 x (RS + RIN) x 20pF + tPWR Where: RS is the source impedance of the input signal; RIN = 1.5k; tPWR of 1s is the power-up time of the device. Note:
tACQ is never less than 1.4s and any source impedance below 300. does not significantly affect the AS1524/ AS1525 AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by placing a 1F capacitor between the positive and negative analog inputs.
(EQ 1)
Selecting AIN1 or AIN2 (AS1525)
Select one of the AS1525 two positive input channels using the CNVST pin (see page 3). If AIN1 is selected (see Figure 19), drive CNVST high to power up the AS1525 and place the track/hold circuitry in track mode with AIN1 connected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1525 then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion.
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AS1524/AS1525
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 19. Single Conversion - AIN1 vs. GND (AS1525), Unipolar Mode AIN+ vs. AIN- (AS1524)
tCONV tACQ CNVST Sampling Instant
SCLK
1
4
8
12
DOUT
High Z
B11 MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
High Z
If AIN2 is selected (see Figure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least 30ns, and then high again. This powers up the AS1525 and places the track/hold circuitry in track mode with AIN2 connected to the positive input capacitor. Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1525 then performs a conversion and shuts down automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Note: If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion.
Selecting Unipolar or Bipolar Conversions (AS1524)
True-differential conversion (with the AS1524 unipolar and bipolar modes) is selected using pin CNVST (see page 3). AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is two's complement. In both modes, the input common mode range can go from GND to VDD. Figure 20. Single Conversion - AIN2 vs. GND (AS1525), Bipolar Mode AIN+ vs. AIN- (AS1524)
tCONV tACQ CNVST Sampling Instant
SCLK
1
4
8
12
DOUT
High Z
B11 MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
High Z
Note: In unipolar and bipolar modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND by more than 50mV. If unipolar mode is selected (see Figure 19), drive CNVST high to power up the AS1524 and place the track/hold circuitry in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1524 then performs a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next conversion. If bipolar mode is selected (see Figure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least 30ns and then high again. This places the track/hold circuitry in track mode with AIN+ and AIN- connected to the input capacitors. Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1524 then performs a conversion and shuts down automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Note: If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next conversion.
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AS1524/AS1525
Datasheet - D e t a i l e d D e s c r i p t i o n
Input Bandwidth
The AS1524/AS1525 input tracking circuitry has a 20MHz small signal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the AS1524/AS1525 sampling rate by using undersampling techniques. Note: To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND - 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD by more than 50mV or be lower than GND by more than 50mV for accurate conversions. Note: If an off-channel analog input voltage exceeds the supply voltages, the input current should be limited to 2mA.
Internal Clock
The AS1524/AS1525 operate from an internal clock, which is accurate within 5% of the 4MHz clock rate. This results in a worst-case conversion time of 3.7s. The internal clock releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to 8MHz.
Output Data Format
Figure 19 on page 12 and Figure 20 on page 12 illustrate the conversion timing for the AS1524/AS1525. The 12-bit conversion result is output in MSB-first format. Data on DOUT transitions on the falling edge of SCLK. All 12 bits must be clocked out before CNVST transitions again. For the AS1524, data is straight binary for unipolar mode and two's complement for bipolar mode. For the AS1525, data is always straight binary.
Transfer Function
Figure 21 on page 13 shows the unipolar transfer function for the AS1524/AS1525. Figure 22 on page 14 shows the bipolar transfer function for the AS1524. Code transitions occur halfway between successive-integer LSB values. Figure 21. AS1524/AS1525 Unipolar Transfer Function
Full Scale = VREF Zero Scale = GND 1 LSB = VREF/4096
11...111 11...110 11....101
Full-Scale Transition
Output Code 00...011 00...010 00...001 00...000 0 1 2 3 FS-3/2 LSB FS
Input Voltage (LSB)
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AS1524/AS1525
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 22. AS1524 Bipolar Transfer Function
Full Scale = VREF/2 -Full Scale = -VREF/2 Zero Scale = 0 1 LSB = VREF/4096
011...111 011...110
000...010 Output Code 000...001 000...000 111...111 111...110 111...101
100...001 100...000 -FS VCOM VREF /2 VIN = AIN+ - AIN0 Input Voltage (LSB) +FS-1 LSB
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AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Automatic Shutdown Mode
With CNVST low, the AS1524/AS1525 default to automatic shutdown (< 0.2A) mode after power-up and between conversions. After detecting a rising edge of CNVST, the AS1524/AS1525 powers up, sets DOUT low, and enters track mode. After detecting a falling edge of CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7s later, the device completes conversion, enters shutdown, and MSB is available at DOUT.
External Reference
An external reference is required for the AS1524/AS1525. Use a 4.7F bypass capacitor for best performance. The reference input structure allows a voltage range of +1V to VDD + 50mV.
Performing a Conversion
1. Use a general-purpose I/O line on the CPU to hold CNVST low between conversions. 2. Drive CNVST high to acquire AIN1(AS1525) or unipolar mode (AS1524). To acquire AIN2 (AS1525) or bipolar mode (AS1524), drive CNVST low and high again. 3. Hold CNVST high for 1.4s. 4. Drive CNVST low and wait approximately 3.7s for conversion to complete. After 3.7s, the MSB is available at DOUT. 5. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the P on SCLK's rising edge.
Standard Interface Connections
The AS1524/AS1525 serial interface is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the processor's serial interface as a master so that the CPU generates the serial clock for the AS1524/ AS1525 and select a clock frequency up to 8MHz.
SPI and Microwire Interface
When using an SPI (Figure 23) or Microwire interface (Figure 24), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 12-bit result from the AS1524/AS1525. DOUT data transitions on the serial clock's falling edge and is clocked into the processor on SCLK's rising edge. The first 8-bit data stream contains the first 8-bits of DOUT starting with the MSB. The second 8-bit data stream contains the remaining four result bits. DOUT then goes high impedance. Figure 23. SPI Serial Interface Connections
8 SCK SCLK 6 I/O CNVST 7 MISO DOUT
SSM
CPU
AS1524/ AS1525
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AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 24. Microwire Serial Interface Connections
8 SK SCLK 6 I/O CNVST 7 SI DOUT
CPU
AS1524/ AS1525
Figure 25. SPI/Microwire Interface Timing Diagram (CPOL = CPHA = 0)
Sampling Instant CNVST 1st Byte Read 2nd Byte Read
SCLK
1
4
8
12
16
DOUT
B11 MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
High Z
QSPI Interface
Using the high-speed QSPI interface (Figure 26) with CPOL = 0 and CPHA = 0, the AS1524/AS1525 support a maximum fSCLK of 8MHz. One 12- to 16-bit reads are necessary to obtain the entire 12-bit result from the AS1524/AS1525. DOUT data transitions on the serial clock's falling edge and is clocked into the processor on SCLK's rising edge. The first 12 bits are the data. DOUT then goes high impedance (see Figure 24). Figure 26. QSPI Serial Interface Connections
8 SCK SCLK 6 CSM CNVST 7 MISO DOUT
SSM
CPU
AS1524/ AS1525
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Revision 1.02
16 - 22
AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 27. QSPI Serial Interface Timing (CPOL = CPHA = 0)
Sampling Instant CNVST
SCLK
1
4
8
12
16
DOUT
B11 MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
High Z
PIC16 and SSP Module and PIC17 Interface
The AS1524/AS1525 are compatible with a PIC16/PIC17 controllers, using the synchronous serial port (SSP) module To establish SPI communication, connect the PIC16/PIC17 controllers as shown in Figure 28 and configure the PIC16/ PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Table 6 on page 18 and Table 7 on page 18. Figure 28. SPI Interface Connections for PIC16/PIC17 Controller
8 SCLK SCLK 6 CNVST CNVST 7 DOUT DOUT
PIC16/ PIC17
AS1524/ AS1525
In SPI mode, the PIC16/PIC17 processor allow 8 bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (see Figure 29) are necessary to obtain the entire 12-bit result from the AS1524/ AS1525. DOUT data transitions on the serial clock's falling edge and is clocked into the processor on SCLK's rising edge. The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the remaining bits, D3 through D0. Figure 29. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1. CKP = 0. SMP = 0, SSPM3:SSPM0 = 0001)
Sampling Instant CNVST 1st Byte Read 2nd Byte Read
SCLK
1
4
8
12
16
DOUT
B11 MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
High Z
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Revision 1.02
17 - 22
AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 6. SSPCON Register Settings Control Bit WCOL SSPOV Bit 7 Bit 6 AS1524/AS1525 Setting X X Synchronous Serial Port Control Register (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial Port Enable 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects FCLK = fOSC / 16.
SSPEN
Bit 5
1
CKP SSPM3:1 SSPM0
Bit 4 Bit 3:1 Bit 0
0 0 1
Table 7. SSPSTAT Register Settings Control Bit SMP CKE D/A P S R/W UA BF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AS1524/AS1525 Setting 0 1 X X X X X X Synchronous Serial Status Register (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
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Revision 1.02
18 - 22
AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Layout and Grounding Considerations
The AS1524/AS1525 require proper layout and design procedures for optimum performance.
! !
Use printed circuit boards; wirewrap boards should not be used. Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other (especially clock traces). Digital traces should not run beneath the AS1524/AS1525. Use a single-point analog ground at GND, separate from the digital ground (see Figure 30). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the AS1524/AS1525 high-speed comparator. Bypass this supply to the single-point analog ground with 0.1F and 4.7F bypass capacitors (see Figure 30). The bypass capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise Power components such as the inductor, converter IC, filter capacitors, and output diode should be placed as close together as possible, and their traces should be kept short, direct, and wide. Keep the voltage feedback network very close to the device, within 5mm (0.2") of the pin. Keep noisy traces, such as those from the pin LX, away from the voltage feedback network and guarded from them using grounded copper traces.
! !
!
!
! !
Figure 30. Recommended Ground Design
+5 or +3V
+5 or +3V
Digital Circuitry
Power Supplies
GND
DGND 4
GND 5 (Optional) +5 or +3V 0.1F
GND
AS1524/ AS1525
1 VDD
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Revision 1.02
19 - 22
AS1524/AS1525
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The devices are available in a 8-pin TDFN (3x3mm) package. Figure 31. 8-pin TDFN (3x3mm) Packagee
D D2 SEE DETAIL B B A L E2/2
aaa C 2x PIN 1 INDEX AREA (D/2 xE/2)
D2/2
E2 K N N-1 e (ND-1) X e
BTM VIEW
E
PIN 1 INDEX AREA (D/2 xE/2)
aaa C
2x TOP VIEW
b ddd bbb C CAB
e DETAIL B e/2
Terminal Tip
ccc C
A3
C
SEATING PLANE
0.08 C
A
Datum A or B EVEN TERMINAL SIDE
Symbol A A1 A3 L1 L2 aaa bbb ccc ddd eee ggg Notes:
Min 0.70 0.00
Typ 0.75 0.02 0.20 REF
Max 0.80 0.05 0.15 0.13
0.15 0.10 0.10 0.05 0.08 0.10
Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
Symbol D BSC E BSC D2 E2 L K b e N ND
Min
Typ 3.00 3.00
A1
SIDE VIEW
Max
1.60 1.35 0.30 0 0.20 0.25
0.40
2.50 1.75 0.50 14 0.35
0.30 0.65 8 4
Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2, 5
1. Figure 31 is shown for illustration only. 2. All dimensions are in millimeters; angles in degrees. 3. Dimensioning and tolerancing conform to ASME Y14.5 M-1994. 4. N is the total number of terminals. 5. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. 6. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 7. ND refers to the maximum number of terminals on side D. 8. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals
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Revision 1.02
20 - 22
AS1524/AS1525
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 8. Table 8. Ordering Information Ordering Code AS1524-BTDT AS1524-BTDR AS1525-BTDT AS1525-BTDR Description 150ksps, 12-Bit, 1-Channel True-Differential ADC 150ksps, 12-Bit, 1-Channel True-Differential ADC 150ksps, 12-Bit, 2-Channel Single-Ended ADC 150ksps, 12-Bit, 2-Channel Single-Ended ADC Delivery Form Tape & Reel Tray Tape & Reel Tray Package 8-pin TDFN (3x3mm) 8-pin TDFN (3x3mm) 8-pin TDFN (3x3mm) 8-pin TDFN (3x3mm)
Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.02
21 - 22
AS1524/AS1525
Datasheet
Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
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Revision 1.02
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